In forming damascene structures in integrated circuit manufacturing processes, the surface condition of the damascene opening is critical for achieving acceptable adhesion and coverage of overlying layers. For example, a dual damascene opening is formed in an inter-metal dielectric (IMD) insulating layer in a series of photolithographic patterning and etching processes, followed by formation of a barrier layer and a metal filling process.
Increasingly, low-K layers are required to reduce signal delay and power loss effects as integrated circuit devices are scaled down. One way this has been accomplished has been to introduce porosity or dopants into the dielectric insulating layer.
As a result, the need for lower dielectric constant materials has resulted in the development of several different types of organic and inorganic low-k materials. In particular, incorporation of low-K materials with dielectric constants less than about 3.0 has become standard practice as semiconductor feature sizes have diminished to less than 0.13 microns. As feature sizes decrease below 0.13 microns, for example to 65 nm and below, materials with dielectric constants less than about 2.5 are required. Several different organic and inorganic low-k materials have been developed and proposed for use in semiconductor devices as insulating material having dielectric constants between about 2.2 and about 3.0.
For example, porous silicon oxide based materials are formed by including a carbon based moiety which forms an Si—O—C type structures which forms a porous structure following deposition and curing or treatment processes. In prior art processes the entire IMD layer has been deposited in a single step process where the entire IMD layer has about the same density or porosity volume throughout the IMD layer.
One problem with using porous low-K IMD materials has been the difficulty of adapting conventional plasma assisted etching processes to reliably and consistently etch openings with acceptable profiles in a low-K IMD layer. The selectivity of plasma etching including the anisotropicity of the etching process becomes more complex as more porosity is introduced into the IMD layer to achieve lower dielectric constants.
For example, etching of the trench portion of a dual damascene opening is critical to overall reliability and performance of the dual damascene structure. Frequently in etching a trench opening overlying one or more vias, the trench structure is patterned directly onto a trench low-K IMD layer frequently resulting less than satisfactory trench etching profiles, for example resulting in a roughened bottom trench portion.
In addition, wet chemical cleaning processes and oxygen ashing processes used in prior art processes to remove sacrificial filling layers protecting the via opening sidewalls exposing the porous low-K IMD layer frequently has a detrimental effect on low-K silicon oxide based (porous) IMD layers, undesirably increasing the dielectric constant following such processes. Other problems with forming dual damascenes in low-K silicon oxide based (porous) IMD layers include photoresist poisoning which is believed to be caused by the absorption and re-emission of photoresist poisoning nitrogen species frequently present from the formation of nitride layers e.g., etch stop layers.
Yet another problem related to forming etched openings in low-K porous IMD layers, is the presence of a relatively rough surface due to the penetration of pore openings at the surface of the etched opening. The micro-roughness at the surface adversely affects the adhesion and coverage of overlying deposited layers, for example barrier layers. As a result, thicker barrier layers, with increased series resistance are required in order to avoid forming barrier layers having pinholes which undesirably allow electromigration of metal into the IMD layer. Further, deposition of seed layers may be non-continuously formed, thereby adversely affecting electro-chemical deposition processes. The various problems with low-K porous IMD layers including an etching profile and etched opening surface condition therefore undesirably affects yield and reliability of integrated circuit semiconductor devices.
There is therefore a need in the integrated circuit manufacturing art to develop a manufacturing process whereby dual damascene structures may be formed without encountering the various problems presented by porous low-K dielectric layers including an opening etching profile and surface condition to improve integrated circuit device yield, performance, and reliability.
It is therefore among the objects of the present invention to provide a manufacturing process whereby dual damascene structures may be formed without encountering the various problems presented by porous low-K dielectric layers including an opening etching profile and surface condition to improve integrated circuit device yield, performance, and reliability, while overcoming other shortcomings of the prior art.